1. Field of the Invention
This invention relates to the field of integrated circuit (IC) fabrication, and particularly to the fabrication of thin film resistors.
2. Description of the Related Art
The ability to integrate high accuracy passive components such as resistors with active devices has become increasingly important. Resistors made from a thin film material have traditionally been employed in Do this context, because they are simple and inexpensive to fabricate.
Conventionally, when thin film resistors (TFRs) are fabricated, they are in contact with the IC""s first level of metallization. This results in different TFRs being at different effective electrical potentials. The effectiveness of a majority of wet etchants is affected by the potential of the material being etched. Therefore, by being at different potentials, the sizes and resistivities of an IC""s TFRs can be affected unequally and unpredictably by wet etch processing steps. This can degrade both resistor accuracy and matching performance.
Conventional TFR fabrication techniques also require that a stack of materials, which includes thin film, barrier, and metal layers, be patterned and etched to define the length of each resistor. Material stacks such as these typically present a step, which interferes with photolithography by either thinning the photoresist in a poorly controlled manner, or by causing reflections. This adversely affects the ability to accurately define resistor length, and thus further degrades resistor accuracy and matching performance.
A thin film resistor fabrication method is presented which overcomes the problems noted above, providing TFRs having well-defined lengths and consistent resistivities.
In accordance with one embodiment of the present method, an IC""s active devices are fabricated on a substrate. A dielectric layer is deposited over these structures, which protects them from the subsequent process steps required to form the TFRs; the dielectric layer is patterned and etched to provide contacts to the existing devices. A layer of thin film material suitable for the formation of TFRs is deposited next, followed by a barrier layer and a first layer of metal. The thin film, barrier, and first metal layer are patterned and etched to form isolated thin film/barrier/metal stacks wherever a TFR is to be located, and a first level of metal interconnections. The first metal layer is then removed from the TFR stacks, and the barrier layer is patterned and etched to provide respective openings which define the active areas of each of the TFRs.
Because the TFR stacks are isolated from the other IC circuitry, their respective effective electrical potentials are all about equal. This reduces the unpredictable effects of subsequent wet etches that can arise when the potentials are unequal. In addition, by removing the first metal layer prior to etching the TFR openings, a thinner stack is presented, which improves the accuracy with which the TFR lengths can be defined.
In a preferred embodiment, a dielectric layer is deposited over the TFR stacks and existing active devices after the first metal layer is removed, to protect the interconnect metal from corrosion and as an adhesion layer for the patterning of the openings which define resistor length.
Once the TFRs are completed, a dielectric layer is preferably deposited, vias to the first layer of metal are patterned and etched, and a second metal layer is deposited, patterned and etched to provide a second layer of metal interconnections.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.